The OpenMP ARB mission is to standardize directive-based multi-language high-level parallelism that is performant, productive and portable.
Jointly defined by a group of major computer hardware and software vendors and major parallel computing user facilities, the OpenMP API is a portable, scalable model that gives shared-memory parallel programmers a simple and flexible interface for developing parallel applications on platforms ranging from embedded systems and accelerator devices to multicore systems and shared-memory systems. The OpenMP ARB owns the OpenMP brand, oversees the OpenMP specification and produces and approves new versions of the specification.
The OpenMP Architecture Review Board
The OpenMP ARB (or just “ARB”) is the non-profit corporation that owns the OpenMP brand, oversees the OpenMP specification and produces and approves new versions of the specification. The ARB helps to organize and fund conferences, workshops, and other related events, and promotes OpenMP. The ARB is composed of permanent and auxiliary members. Permanent members are vendors who have a long-term interest in creating products for OpenMP. Auxiliary members are normally organizations with an interest in the standard but that do not create or sell OpenMP products.
Contact the ARB at the e-mail address info AT openmp.org to submit questions about membership, business issues, and the like. All other questions about the OpenMP API should be directed through the User Forums. The ARB, like most non-profit corporations, has corporate officers (CEO, CFO, and Secretary) and a Board of Directors. The officers are responsible for the day-to-day business of the corporation. The Board of Directors is responsible for setting long-term corporate direction and approving large or unusual expenditures; it acts as an oversight and governance body for the corporation.
Read the OpenMP Welcome Guide for more information about OpenMP membership and history.
Permanent Members of the ARB:
- AMD (Greg Stoner)
- ARM (Chris Adeniyi-Jones)
- Cray (Luiz DeRose)
- Fujitsu (Eiji Yamanaka)
- HP (Sujoy Saraswati)
- IBM (Kelvin Li)
- Intel (Xinmin Tian)
- Micron (Kirby Collins)
- NEC (Kazuhiro Kusano)
- NVIDIA (Jeff Larkin)
- Oracle Corporation (Nawal Copty)
- Red Hat (Matt Newsome)
- Texas Instruments (Andy Fritsch)
Auxiliary Members of the ARB:
- Argonne National Laboratory (Kalyan Kumaran)
- ASC/Lawrence Livermore National Laboratory (Bronis R. de Supinski)
- Barcelona Supercomputing Center (Xavier Martorell)
- cOMPunity (Barbara Chapman/Yonghong Yan)
- Edinburgh Parallel Computing Centre (EPCC) (Mark Bull)
- Los Alamos National Laboratory (David Montoya)
- Lawrence Berkeley National Laboratory (Alice Koniges/Helen He)
- NASA (Henry Jin)
- Oak Ridge National Laboratory (Oscar Hernandez)
- RWTH Aachen University (Dieter an Mey)
- Sandia National Laboratory (Stephen Olivier)
- Texas Advanced Computing Center (Kent Milfeld)
- University of Houston (Barbara Chapman/Deepak Eachempati)
Sanjiv Shah, Intel –– Chair (through 2015) is the director of the Performance, Analysis and Threading Lab in the software group at Intel. Sanjiv specializes in parallel computing and his lab produces tools and libraries for parallel software, performance and correctness analysis. Sanjiv has been extensively involved with the OpenMP specifications from the beginning and implemented the first Fortran and C/C++ compilers supporting OpenMP (and precursors of OpenMP). He is a former CEO of the OpenMP Architecture Review Board and continues to serve on its Board of Directors.
Josh Simons, VMware, Inc. (through 2017) With over 20 years of experience in High Performance Computing, Josh currently leads an effort to bring the full value of virtualization to HPC. Previously, he was a Distinguished Engineer at Sun Microsystems with broad responsibilities for HPC direction and strategy. He joined Sun in 1996 from Thinking Machines Corporation, a pioneering company in the area of Massively Parallel Processors (MPPs), where he held a variety of technical positions. Josh has worked on developer tools for distributed parallel computing, including language and compiler design, scalable parallel debugger design and development, and MPI. He has also worked in the areas of 3D graphics, image processing, and realtime device control. Josh has an undergraduate degree in Engineering from Harvard College and a Masters in Computer Science from Harvard University. He has served as a member of the Board of Directors since 2002.
Andy Fritsch, Texas Instruments (through 2015) is the Manager of Foundational Tools for Texas Instruments. In his role, Andy manages development of tools for TI’s processors across many product areas including DSPs, microcontrollers and automotive. His responsibilities include compilers, hardware debug probes/platforms, simulators, tools product management and applications support. Previously, he was a silicon development program manager with responsibility for architecture, specification, design, test and verification, packaging, qualification and software platforms for TI’s C6000 DSPs. Andy started his career at TI developing real time geophysical applications and RTOS’s. He has also held roles in applications engineering management, partner relationship management and in software and hardware development. Andy has a BS in Applied Mathematics from the University of Tulsa.
Partha Tirumalai, Oracle (through 2017) is a Senior Principal Engineer and Technical Advisor in the Systems Group of Oracle Corporation. His interests are in processor architecture, optimizing and parallelizing compilers, application performance, and high performance computing systems. He has authored numerous papers and has received a number of patents in these areas. Prior to joining Oracle, he was a Distinguished Engineer at Sun Microsystems, and earlier worked as a Senior Research Scientist at Hewlett-Packard Laboratories. Partha holds a B. Tech degree in Electrical Engineering from I.I.T., Madras, and M.S. and Ph.D. degrees in Computer Science from Northwestern University.
Dieter an Mey (through 2016) leads the high performance computing team of RWTH Aachen University’s Center for Computing and Communication in Germany. He studied Mathematics and Computer Science in Aachen and by now has a 30+ year track record in HPC with a focus on user support and services. Starting with vectorization and message passing, he and his group are actively participating in the OpenMP community since the first OpenMP specification was released. He is co-author of numerous publications on OpenMP programming and productivity.
CEO: Michael Wong is the IBM and Canadian representative to the C++ Standard, OpenMP Committee and Software Transactional Memory group. He is the co-author of a number of C++0x/OpenMP/STM features. He is the past C++ team lead to IBM´s XL C++ compiler, C compiler and has been designing C++ compilers for fifteen years. He is currently leading the C++0x deployment as a senior technical lead for IBM. His current research interest is in the area of parallel programming, C++ benchmark performance, object model, generic programming and template metaprogramming. He is a frequent speaker at various technical conferences and serves on the Programming Committee of Boost, and IWOMP. He holds a B.Sc from University of Toronto, and a Masters in Mathematics from University of Waterloo.
CFO: Dave Poulsen, Intel Dave Poulsen received a Ph.D. degree in Electrical and Computer Engineering from the University of Illinois in 1994. He then joined Kuck and Associates, Inc. (KAI) where he worked on parallelizing compilers, as well as KAI’s OpenMP compiler and threading correctness/performance tools. With KAI’s acquisition by Intel in 2000, he worked on integrating OpenMP and KAI’s threading tools technologies into Intel’s software product line-up. After a brief stint working on Intel’s MPI library product, Dave became the project lead for Intel’s new Threading Building Blocks (TBB) product. Dave is currently the engineering manager of the Threading Runtimes team in the Performance, Analysis and Threading Lab at Intel, which develops their OpenMP runtime libraries as well as TBB. Prior to working on his Ph.D., Dave worked for IBM in upstate New York, where he was a processor designer for 3090-class mainframe CPUs. And, he’s very neat and well organized, and knows how to balance a checkbook, which is why he is CFO.
Secretary: Christian Terboven, RWTH Aachen University
Marketing Coordinator: Matthijs van Waveren is the Fujitsu representative to the OpenMP ARB and to the SPEC High-Performance Group. He has contributed to the development of several SPEC benchmarks and of a number of OpenMP features. He is member of the Board of SPEC, and has received several SPECtacular awards. He holds a PhD from the University of Amsterdam.
Chair of the Language Committee: Bronis R. de Supinski is the principal investigator and leader of the Exascale Computing Technlogies (ExaCT) project and the co-leader of the Advanced Simulation and Computing (ASC) program’s Application Development Environment and Performance Team (ADEPT) at Lawrence Livermore National Laboratory (LLNL). He is also an Adjunct Associate Professor in the Department of Computer Science and Engineering at Texas A&M University. Bronis earned his Ph.D. in Computer Science from the University of Virginia in 1998 and he joined LLNL’s Center for Applied Scientific Computing (CASC) in July 1998. Currently, his projects include scalable debugging methods, investigations into mechanisms and tools to improve memory performance, applications of data mining techniques to tools for large-scale systems, resiliency techniques, a variety of optimization techniques and tools for MPI and several issues with OpenMP, including its memory model and tool support. He pursues the last set of topics as the Chair of the OpenMP Language Committee. Throughout his career, Bronis has won several awards, including the prestigious Gordon Bell Prize in 2005 and 2006.
Webmaster: Richard Friedman is a freelance technical writer/editor and web designer, and lives in Oakland, CA. For 3 decades he was a Fortran and systems programmer on the IBM 650, IBM 7094, CDC 6600/7600, Cray 1, Cyber 205, before becoming a full-time technical writer at Sun Microsystems, specializing in compilers and high performance computing. Visit his website at rchrd.com.